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Integrated Circuit Systems, Inc.
ICS85314I-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
FEATURES
* 5 differential 2.5V/3.3V LVPECL outputs * Selectable differential CLK0, nCLK0 or LVCMOS inputs * CLK0, nCLK0 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL * CLK1 can accept the following input levels: LVCMOS or LVTTL * Maximum output frequency: 700MHz * Translates any single-ended input signal to 3.3V LVPECL levels with resistor bias on nCLK input * Output skew: 30ps (maximum), TSSOP package 50ps (maximum), SOIC package * Part-to-part skew: 350ps (maximum) * Propagation delay: 1.8ns (maximum) * RMS phase jitter @ 155.52MHz (12kHz - 20MHz): 0.05ps (typical) * LVPECL mode operating voltage supply range: VCC = 2.375V to 3.8V, VEE = 0V * -40C to 85C ambient operating temperature * Available in both standard and lead-free RoHS-compliant packages
GENERAL DESCRIPTION
The ICS85314I-01 is a low skew, high performance 1-to-5 Differential-to-2.5V/3.3V LVPECL HiPerClockSTM Fanout Buffer and a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS85314I-01 has two selectable clock inputs. The CLK0, nCLK0 pair can accept most standard differential input levels. The single-ended CLK1 can accept LVCMOS or LVTTL input levels. The clock enable is internally synchronized to eliminate runt clock pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin.
IC S
Guaranteed output and part-to-part skew characteristics make the ICS85314I-01 ideal for those applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
nCLK_EN D Q LE CLK0 nCLK0 CLK1
PIN ASSIGNMENT
Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 Q4 nQ4 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC nCLK_EN VCC nc CLK1 CLK0 nCLK0 nc CLK_SEL VEE
00 1
1
Q0 nQ0 Q1 nQ1
CLK_SEL Q2 nQ2 Q3 nQ3 Q4 nQ4
ICS85314I-01
20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm Package Body G Package Top View
ICS85314I-01
20-Lead SOIC 7.5mm x 12.8mm x 2.3mm Package Body M Package Top View
85314BGI-01
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1
REV. E SEPTEMBER 23, 2005
Integrated Circuit Systems, Inc.
ICS85314I-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
Type Description Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Negative supply pin. Clock select input. When HIGH, selects CLK1 input. Pulldown When LOW, selects CLK0, nCLK0 inputs. LVTTL / LVCMOS interface levels. No connect. Pullup Inver ting differential clock input. Pulldown Non-inver ting differential clock input. Pulldown Clock input. LVTTL / LVCMOS interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3, 4 5, 6 7, 8 9, 10 11 12 13, 17 14 15 16 18, 20 Name Q0, nQ0 Q1, nQ1 Q2, nQ2 Q3, nQ3 Q4, nQ4 VEE CLK_SEL nc nCLK0 CLK0 CLK1 VCC Output Output Output Output Output Power Input Unused Input Input Input Power
Positive supply pins. Synchronizing clock enable. When LOW, clock outputs follow clock 19 nCLK_EN Input Pulldown input. When HIGH, Q outputs are forced low, nQ outputs are forced high. LVTTL / LVCMOS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
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REV. E SEPTEMBER 23, 2005
Integrated Circuit Systems, Inc.
ICS85314I-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
Inputs Outputs Selected Source CLK0, nCLK0 CLK1 CLK0, nCLK0 Q0:Q4 Enabled Enabled Disabled; LOW nQ0:nQ4 Enabled Enabled Disabled; HIGH Disabled; HIGH
TABLE 3A. CONTROL INPUT FUNCTION TABLE
nCLK_EN 0 0 1 CLK_SEL 0 1 0
1 1 CLK1 Disabled; LOW After nCLK_EN switches, the clock outputs are disabled or enabled following a falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK0, nCLK0 and CLK1 inputs as described in Table 3B.
Disabled
Enabled
nCLK0 CLK0, CLK1
nCLK_EN
nQ0:nQ4 Q0:Q4
FIGURE 1. nCLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs CLK0 or CLK1 0 1 nCLK0 1 0 Q0:Q4 LOW HIGH Outputs nQ0:nQ4 HIGH LOW Input to Output Mode Differential to Differential Differential to Differential Polarity Non Inver ting Non Inver ting
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REV. E SEPTEMBER 23, 2005
Integrated Circuit Systems, Inc.
ICS85314I-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
4.6V -0.5V to VCC + 0.5V 50mA 100mA 73.2C/W (0 lfpm) 46.2C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA 20 Lead TSSOP 20 Lead SOIC Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0V, TA = -40C TO 85C
Symbol VCC IEE Parameter Power Supply Voltage Power Supply Current Test Conditions Minimum 2.375 Typical 3.3 Maximum 3.8 80 Units V mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0V, TA = -40C TO 85C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current nCLK_EN, CLK_SEL CLK1 nCLK_EN, CLK_SEL CLK1 CLK1, CLK_SEL, nCLK_EN CLK1, CLK_SEL, nCLK_EN Test Conditions Minimum 2 2 -0.3 -0.3 VIN = VCC = 3.8V VCC = 3.8V, VIN = 0V -5 Typical Maximum VCC + 0.3 VCC + 0.3 0.8 1.3 150 Units V V V V A A
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0V, TA = -40C TO 85C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current nCLK0 CLK0 nCLK0 CLK0 Test Conditions VCC = VIN = 3.8V VCC = VIN = 3.8V VCC = 3.8V, VIN = 0V VCC = 3.8V, VIN = 0V -150 -5 1.3 VCC - 0.85 Minimum Typical Maximum 5 150 Units A A A A V V
Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; 0.5 VCMR NOTE 1, 2 NOTE 1: For single ended applications the maximum input voltage for CLK0, nCLK0 is VCC + 0.3V. NOTE 2: Common mode voltage is defined as VIH.
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REV. E SEPTEMBER 23, 2005
Integrated Circuit Systems, Inc.
ICS85314I-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
Test Conditions Minimum VCC - 1.4 VCC - 2.0 0.6 Typical Maximum VCC - 0.9 VCC - 1.7 1.0 Units V V V
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0V, TA = -40C TO 85C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50 to VCC - 2V.
TABLE 5. AC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0V, TA = -40C TO 85C
Symbol Parameter fMAX tjit (O) tpLH t sk(o) t sk(pp) t R / tF odc Output Frequency CLK0, nCLK0 CLK1 Integration Range: (12kHz - 20MHz) 1.0 0.05 1. 4 1.8 30 50 350 20% to 80% CLK0, nCLK0 700MHz 200 45 700 55 55 Test Conditions Minimum Typical Maximum 700 300 Units MHz MHz ps ns ps ps ps ps % %
RMS Phase Jitter (Random); NOTE 5 Propagation Delay, Low to High; NOTE 1 Output Skew; NOTE 3, 6 TSSOP Package SOIC Package
Par t-to-Par t Skew; NOTE 4, 6 Output Rise/Fall Time Output Duty Cycle
CLK1 250MHz 45 All parameters measured at fMAX unless noted otherwise. The cycle-to-cycle jitter on the input will equal the jitter on the output. The par t does not add jitter NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Measured from VCC/2 input crossing point to the differential output crossing point. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 5: Please refer to the Phase Noise Plot. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
85314BGI-01
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REV. E SEPTEMBER 23, 2005
Integrated Circuit Systems, Inc.
ICS85314I-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
TYPICAL PHASE NOISE AT 155.52MHZ
0 -10 -20 -30 -40 -50
155.52MHz
RMS Phase Jitter (Random) 12kHz to 20MHz = 0.05ps (typical)
NOISE POWER dBc Hz
-60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M
Raw Phase Noise Data
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OFFSET FREQUENCY (HZ)
REV. E SEPTEMBER 23, 2005
Integrated Circuit Systems, Inc.
ICS85314I-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2V
VCC
Qx
SCOPE
VCC
nCLK0
LVPECL
nQx
V CLK0
PP
Cross Points
V
CMR
VEE
-1.8V -0.375V
VEE
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx Qx nQy Qy
PART 1 nQx Qx PART 2 nQy Qy
tsk(o)
tsk(o)
OUTPUT SKEW
PART-TO-PART SKEW
Phase Noise Plot
Noise Power
nQ0:nQ4 Q0:Q4
Phase Noise Mask
t PW
t
PERIOD
f1
Offset Frequency
f2
odc =
t PW t PERIOD
x 100%
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
85314BGI-01
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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REV. E SEPTEMBER 23, 2005
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ICS85314I-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
nCLK0 CLK0 nQ0:nQ4 Q0:Q4
tPD
CLK1 nQ0:nQ4 Q0:Q4
tPD
PROPAGATION DELAY (DIFFERENTIAL INPUT)
PROPAGATION DELAY (LVCMOS INPUT)
80% Clock Outputs
80% VSW I N G
20% tR tF
20%
OUTPUT RISE/FALL TIME
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REV. E SEPTEMBER 23, 2005
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ICS85314I-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u
R2 1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS:
CLK INPUT: For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the CLK input to ground. CLK/nCLK INPUT: For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from CLK to ground. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used.
85314BGI-01
LVPECL OUTPUT All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.
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REV. E SEPTEMBER 23, 2005
Integrated Circuit Systems, Inc.
ICS85314I-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V 3.3V LVDS_Driv er R1 100 Zo = 50 Ohm Zo = 50 Ohm
CLK
nCLK
Receiv er
FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY 3.3V LVDS DRIVER
3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 R3 125 R4 125 CLK Zo = 50 Ohm C2 nCLK HiPerClockS Input
R5 100 - 200
R6 100 - 200
R1 84
R2 84
R5,R6 locate near the driver pin.
FIGURE 3E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER WITH AC COUPLE
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REV. E SEPTEMBER 23, 2005
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ICS85314I-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive
3.3V
Zo = 50
125
FOUT FIN
125
Zo = 50
Zo = 50 50 1 Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FOUT
FIN
Zo = 50 84 84
RTT =
FIGURE 4A. LVPECL OUTPUT TERMINATION
FIGURE 4B. LVPECL OUTPUT TERMINATION
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REV. E SEPTEMBER 23, 2005
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ICS85314I-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
close to ground level. The R3 in Figure 5B can be eliminated and the termination is shown in Figure 5C.
TERMINATION
FOR
2.5V LVPECL OUTPUT
Figure 5A and Figure 5B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very
2.5V
2.5V 2.5V VCC=2.5V R1 250 Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R2 62.5 R4 62.5 R3 250
VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
R3 18
FIGURE 5A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 5B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
FIGURE 5C. 2.5V LVPECL TERMINATION EXAMPLE
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REV. E SEPTEMBER 23, 2005
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ICS85314I-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85314I-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS85314I-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.8V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 80mA = 304mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 5 * 30.2mW = 151mW
Total Power_MAX (3.465V, with all outputs switching) = 304mW + 151mW = 455mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6C/W per Table 6A below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.455W * 66.6C/W = 115C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6A. THERMAL RESISTANCE JA
FOR
20-PIN TSSOP, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 114.5C/W 98.0C/W 88.0C/W Multi-Layer PCB, JEDEC Standard Test Boards 73.2C/W 66.6C/W 63.5C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 6B. THERMAL RESISTANCE JA
FOR
20-PIN SOIC, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 83.2C/W 65.7C/W 57.5C/W Multi-Layer PCB, JEDEC Standard Test Boards 46.2C/W 39.7C/W 36.8C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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3. Calculations and Equations.
ICS85314I-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
LVPECL output driver circuit and termination are shown in Figure 6.
VCC
Q1
VOUT RL 50 VCC - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CC
*
For logic high, VOUT = V (V
CC_MAX
OH_MAX
=V
CC_MAX
- 1.0V
-V
OH_MAX
) = 1.0V =V - 1.7V
*
For logic low, VOUT = V (V
CC_MAX
OL_MAX
CC_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V - (V - 2V))/R ] * (V
L
OH_MAX
CC_MAX
CC_MAX
-V
OH_MAX
) = [(2V - (V
CC_MAX
-V
OH_MAX
))/R ] * (V
L
CC_MAX
-V
OH_MAX
)=
[(2V - 1V)/50] * 1V = 20.0mW
Pd_L = [(V
OL_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
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REV. E SEPTEMBER 23, 2005
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ICS85314I-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER RELIABILITY INFORMATION
TABLE 7A. JAVS. AIR FLOW TABLE
FOR
20 LEAD TSSOP
by Velocity (Linear Feet per Minute)
JA
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 114.5C/W 73.2C/W
200
98.0C/W 66.6C/W
500
88.0C/W 63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 7B.
JAVS. AIR FLOW TABLE FOR 20 LEAD SOIC
by Velocity (Linear Feet per Minute)
JA
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 83.2C/W 46.2C/W
200
65.7C/W 39.7C/W
500
57.5C/W 36.8C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS85314I-01 is: 674 Compatible to part number MC100LVEL14
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ICS85314I-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
20 LEAD TSSOP
PACKAGE OUTLINE - G SUFFIX
FOR
TABLE 8A. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 6.40 6.40 BASIC 4.50 Millimeters Minimum 20 1.20 0.15 1.05 0.30 0.20 6.60 Maximum
Reference Document: JEDEC Publication 95, MO-153 www.icst.com/products/hiperclocks.html
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REV. E SEPTEMBER 23, 2005
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ICS85314I-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
20 LEAD SOIC
PACKAGE OUTLINE - M SUFFIX
FOR
TABLE 8B. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 B C D E e H h L 10.00 0.25 0.40 0 -0.10 2.05 0.33 0.18 12.60 7.40 1.27 BASIC 10.65 0.75 1.27 8 Millimeters Minimum 20 2.65 -2.55 0.51 0.32 13.00 7.60 Maximum
Reference Document: JEDEC Publication 95, MS-013, MO-119
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ICS85314I-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
Marking ICS85314BI01 ICS85314BI01 ICS5314BI01L ICS5314BI01L Package 20 lead TSSOP 20 lead TSSOP 20 lead "Lead-Free" TSSOP 20 lead "Lead-Free" TSSOP 20 lead SOIC 20 lead SOIC 20 lead "Lead-Free" SOIC 20 lead "Lead-Free" SOIC Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel tube 1000 tape & reel tube 1000 tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS85314BGI-01 ICS85314BGI-01T ICS85314BGI-01LF ICS85314BGI-01LFT ICS85314BMI-01 ICS85314BMI-01T ICS85314BMI-01LF ICS85314BMI-01LFT
ICS85314BI-01 ICS85314BI-01 TBD TB D
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 85314BGI-01
www.icst.com/products/hiperclocks.html
18
REV. E SEPTEMBER 23, 2005
Integrated Circuit Systems, Inc.
ICS85314I-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
REVISION HISTORY SHEET
Rev A
Table
B
T2 T5
C
T5
Page 7 8 9 15 1 2 5 6 8 9 1 4 5 7 1 5 5 9
D
T5 T4D
E T9
18
Description of Change Updated Figure 2, Single Ended Signal Diagram. Added "Termination for 2.5V LVPECL Outputs" section. Added "Differential Input Interface" section. Corrected Order Number and Marking from Rev. A to Rev. B. Added Phase Noise Bullet to Features section. Changed CIN from 4pF max. to 4pF typical. AC Characteristics Table - added RMS Phase Jitter. Added Phase Jitter Plot. Updated Termination for 3.3V LVPECL Output diagrams. Updated Termination for 2.5V LVPECL Output section. Features section - added SOIC package output skew. Absolute Maximum Ratings - added SOIC Package Thermal Impedance. AC Characteristics table - added SOIC package for Output Skew. Parameter Measurement Information - added Par t-to-Par t Skew and RMS Phase Jitter Diagrams. Features section - changed Par t-to-Par t Skew from 250ps max. to 350ps max. AC Characteristics table - changed Par t-to-Par t Skew from 250ps max. to 350ps max. LVPECL DC Characteristics Table - changed VOH max from VCC - 1.0V to VCC - 0.9V. Application Information Section - added Recommendations for Unused Input and Output Pins. Added TSSOP Lead-Free par t number.
Date 3/31/03
8/11/04
3/22/05
5/24/05
9/23/05
85314BGI-01
www.icst.com/products/hiperclocks.html
19
REV. E SEPTEMBER 23, 2005

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